Threedimensional device simulation is mandatory for investigations on real threedimensional structures because these structures cannot be described by twodimensional cuts. As an example, Fig. 2.1 shows the threedimensional structure of a Lateral Trench LDMOSFET. The figure shows the device at breakdown with . The gate is built by a trench whereas the channel forms at the sidewall of the trench gate vertically in the device. Due to the superjunction concept the drift area is fully depleted at breakdown. The potential is uniformly distributed to account for the Reduced Surface Field (RESURF) effect.
Furthermore, threedimensional simulations are mandatory when feature sizes become so small that the threedimensional shape of geometries cannot be neglected. Thus twodimensional simulations are no more reliable. A frequently cited example is the narrow channel effect of MOS transistors which are normally simulated in twodimensional cuts. When the width of the channel becomes comparable to its length, the current path becomes clearly threedimensional.
Another more obvious example is the temperature profile in real devices. Twodimensional simulations cannot predict temperature profiles very well, because they do not take all cooling plates and directions of the heat flow into account. As an example Fig. 2.2 shows the geometry of a body contacted SOI MOS transistor. The gate is Tshaped and its length is and the width . The gate oxide thickness is . The transistor is surrounded by a rectangular silicon area of width which has been used here only to increase the cooling area and therefore to make the resulting temperature profile more visible.
Fig. 2.3 shows the result of a threedimensional simulation. At the thermal contacts was applied. The temperature profile is clearly threedimensional contrary to the assumptions made for twodimensional simulations. At the end of the gate in direction the temperature is lower than in the middle.
Fig. 2.4(a) shows the result of a twodimensional simulation performed for the cut AA depicted in Fig. 2.2. As a comparison, in Fig. 2.4(b) the same cut AA is shown for the threedimensional simulation of Fig. 2.3. As expected, the highest temperature appears in the channel below the gate and decreases with increasing lateral distance to the channel. Because the thermal resistance of SiO2 is much higher than that of silicon, a high temperature range is supplied by the gate.

To clearly stress out this result the temperature at the surface of the silicon segment of both the twodimensional simulation ( Fig. 2.4(a)) and the cut of the threedimensional result (Fig. 2.4(b)) is shown in Fig. 2.5. It can be clearly seen, that the twodimensional simulation predicts a much higher temperature compared to the threedimensional one. The maximal temperature in the channel below the gate is calculated as for the twodimensional case and as for the threedimensional case. Therefore, the error of the temperature increase due to self heating made by the twodimensional simulation is about below the gate and about at the side.
Fig. 2.6 and Fig. 2.7 show the temperature profile of a body contacted SOI MOS transistor with a gate width of and , respectively. Both figures show a threedimensional shape of the temperature inside the device. But from these figures one can clearly see the increasing importance of threedimensional simulations with decreasing feature sizes of the devices. Twodimensional simulations are no more accurate enough, not even for long devices.
Robert Klima 20030206